Abstract: MRAM is now coming into its own as a disruptive technology. With over 100 million units shipped, it has already brought unparalleled performance levels to many industrial applications over the last decade. Recent advances have led to STT-MRAM emerging as a practical technology for manufacturing. Visionary companies are using it today to create a new class of high-performance, low-latency storage systems. Demand for this technology in embedded SoC applications on leading-edge semiconductor processes has also led to major investments by foundries and manufacturing equipment companies to add it to their portfolios. Discrete STT-MRAM has recently broken the Gb density barrier, both reducing bit cost and increasing the range of applications. These are just the first steps in unlocking MRAM’s disruptive potential for taking advanced computing architectures to new performance levels and meeting the need for simpler, smaller, and faster 5G-connected IoT devices.
Abstract: STT (Spin-Transfer Torque) MRAM offers excellent properties for a wide variety of applications, including embedded memory, cache memory, standalone memory, and storage-class memory. However, process difficulties remain in achieving the small write current, high MR ratio/low RA product, and high thermal stability required to take STT-MAM into high-volume manufacturing. New process-vapor deposition (PVD) tools deliver much higher performance for forming complex multi-stack thin films. Process modules can be flexibly configured or added to accommodate applications at different stages from R&D to high volume production. The tools also offer great flexibility for new techniques such as perpendicular magnetization, and stability for wafer uniformity and tool marathon run performance.
Abstract: With all major foundries offering STT MRAM technology at 40-22nm nodes, the development focus is now shifted to scaling beyond these nodes, and to enable newer applications by improving performance. Scaling typically requires reducing the RA of the MgO tunneling barrier while still maintaining the reliability of the device, as well as reducing the pitch of the bits in memory arrays with similar ppm level yields as demonstrated in current products. Some of the key issues and potential solutions, in terms of materials and process engineering of stacks, to achieve these goals are discussed.