Jeff Ohshima is a member of the technology executive team at KIOXIA, where he focuses on SSD development and applications engineering. He was previously VP Memory Technology Executive at Toshiba America Electronic Components focused on flash memory with an emphasis on SSDs. He has also been Senior Manager R&D in the advanced NAND flash memory design department, responsible for 70 nm, 56 nm, 43 nm, and 32 nm part design. He has worked on memory at Toshiba and KIOXIA for over 35 years, including 20 years on DRAM where he acted as a lead design for application specific memories and did technical marketing. Jeff has served as a visiting research scientist at Stanford University. He holds a BSEE and MSEE from Tokyo's Keio University.
Scott Nelson holds the position of Executive Vice President and Chief Marketing Officer at KIOXIA America, Inc. A 35-year industry veteran, he is responsible for the sales and marketing of KIOXIA's cutting-edge BiCS FLASH™ 3D flash memory solutions and robust SSD products. He also oversees these efforts for the company's complete lines of e-MMC, UFS, and SLC solutions and flash-based memory cards. Under his direction, KIOXIA's high-density, scalable storage technology continues to enable new applications in existing markets such as data center, hyperscale, mobile/compute and gaming to a variety of emerging markets such as artificial intelligence, virtual reality, augmented reality, and advanced driver assistance systems. Scott has held numerous sales, marketing and product management positions within the company's Memory business unit, leading up to his current position. He holds a Bachelor of Arts degree in business and operations management from California State University at Fullerton, and an MBA from Pepperdine University.
As the inventor of NAND flash memory 35 years ago, KIOXIA continues to innovate flash technology and change the world and how we live. Technologies like 5G, the cloud and IoT, as well as applications including AI/ML, medical, and databases, help drive demand for flash to new heights. New flash memory technologies are needed to address these demands, as well as enable new and exciting applications. KIOXIA is developing NAND flash technologies that continue to make memory faster, increase bits per cell, and innovate new architectures and new types of memory. SSDs are transforming with interfaces, such as PCIe, Ethernet and CXL, EDSFF form factors, and bring exciting aspects of performance, while Software-Enabled Flash technology helps drive new levels of efficiency and TCO for hyperscale data centers.
Dr. Luca Fasoli is Senior Vice President of Silicon Technology and Manufacturing at Western Digital. He is responsible for the strategy and the development of Western Digital solid-state memory technologies. Previously, he held engineering management positions at Waferscale Integration, STMicroelectronics, Matrix Semiconductor and at SanDisk after its acquisition of Matrix.
As a 25-year industry veteran and IEEE Senior Member, Dr. Fasoli has worked on a variety of non-volatile memory technologies and solid-state storage products, leading product development teams from concept definition to mass production.
Dr. Fasoli has published many technical papers and holds more than 90 U.S. patents. He earned a doctorate and master's degree in Electronic Engineering from the Polytechnic University of Milan, and completed the Engineering Leadership Professional Program at UC Berkeley. He is based at the company's Milpitas, CA location.
Khurram Ismail is Senior Vice President of Engineering for Western Digital's Flash Business Unit. In this role, Ismail oversees product development of the Flash Business Unit's growing portfolio of SSDs, embedded, retail, consumer and removable products. He leads multi-disciplinary product development teams, including ASIC, firmware, hardware, validation, and system design engineers, who are focused on vertically integrating Western Digital Flash technology with engineering solutions to serve a wide range of customers from OEMs to consumers.
Ismail brings 22 years of engineering and management experience in the Flash industry with a unique combination of business acumen, technical understanding, and systems development gained as an engineer and executive at companies including Western Digital, SanDisk and Micron.
His prior roles include product development in client and embedded, applications engineering, supporting DRAM/Flash, and product and test engineering. Ismail earned a bachelor's in Electrical Engineering from Northern Arizona University. Khurram Ismail is based at the company's San Jose, CA headquarters.
Since its conception more than 35 years ago, NAND Flash has transformed industries, fueled innovations and disrupted markets. From mobile devices and connected vehicles to gaming and data centers, Flash is at the core. Virtually every market is growing in ways that demand more than just faster and greater capacities of Flash. In this keynote, Western Digital will look at the various approaches to 3D NAND Flash scaling and discuss how an optimal combination of vertical and lateral scaling is needed to achieve an efficient capital investment strategy. Continuous innovation and fully integrated design and device architecture have enabled achieving consistently increasing performance and reliability over multiple NAND generations. We see no end in sight to 3D NAND Flash scaling and its potential widespread applications. As NAND technology evolves, vertical system integration and intimate device knowledge are mandatory to deliver products that will meet future application needs for decades to come.
Dr. Hongbin Zhu is the Vice President of Research & Development at YMTC, focusing on product process development. Dr. Zhu has over 20 years of experience in semiconductor process research and development, with expertise in process improvement and development, equipment and material development, and process integration.
Dr. Zhu received his Ph.D. in chemical engineering from the University of Arizona and holds more than 100 patents.
Since its invention 35 years ago, NAND flash memory has been widely applied in smartphones, PCs, tablets, and servers due to its performance and cost advantages. As the market keeps evolving to meet customers' higher service level requirements, storage suppliers have been pursuing NAND device innovation into more layers with more advanced architectures to achieve lower bit cost and better system performance. In 2018, YMTC debuted its innovative Xtacking® technology at FMS, pioneering a brand-new 3D NAND infrastructure which resolved bottlenecks in bit density, performance, and time-to-market as compared with conventional flash memory. YMTC's Xtacking® technology is now recognized by customers worldwide for its derivative system solutions. Meanwhile, the bonding technology of CMOS peripheral circuitry and the NAND array has also been recognized by many players in the industry. This presentation will introduce YMTC's vision for the future of Xtacking® technology, and a new generation of NAND flash memory products.
Jihyo Lee is CEO and co-founder of FADU Technologies. He is a former partner at Bain & Company, and a successful serial entrepreneur involved in multiple businesses in technology, telecom, and energy. As its CEO, he has established FADU as a fabless semiconductor innovator, uniting exceptional industry talent to create a revolution in data center and storage for next-generation computing architectures.
Ross Stenfort is a member of Meta's Storage Hardware team. He has over 20 years of experience developing and bringing leading edge storage products to market. Ross works closely with industry partners and standards organizations including NVM Express, SNIA/EDSFF, and Open Compute Project (OCP). With experience including ASIC design, he has an appreciation for the challenges facing SSD providers with delivering performance and QoS within a shrinking power envelope. Ross is an inventor of over 40 patents.
Join FADU's CEO, Jihyo Lee, in conversation with Ross Stenfort, Hardware Storage Engineer at Meta. These two storage experts will discuss design considerations for SSDs in Hyperscale Data Centers, elaborating on key challenges including power envelopes, write amplification, and designing for Quality of Service (QoS). Ross will share views on system-level challenges seen in the industry, and industry-wide efforts underway to optimize designs to best match various system configurations. Jihyo will address the architectural changes in SSD controllers, and therefore in SSDs, for optimization to support power envelopes, write amplification, and QoS.
Sanjay's Client Storage Group and the CMD team develops and delivers world-class and industry-leading storage solutions for the PC segment. Over a 30-plus year career, Sanjay has held a variety of technical and management positions in component and systems engineering, marketing, sales, and business development. As GM, Sanjay leads a large cross-functional team that owns all aspects of the business from inception to HVM at all major PC OEMs. Sanjay is an author on 25 patents.
Jungdal Choi is Executive VP and Head of NAND Development at SK hynix, overseeing 4D NAND development using 3D CTF design paired with PUC(Periphery Under Cell) technology. Throughout his career, which began with EEPROM circuit design in 1986, he was involved in the development of various types of memories, including EEPROM, such as SRAM, mask ROM, and NAND. In particular, he developed the industry's first 32Gb CTF NAND in 2007, which now serves as the backbone of 3D NAND products. With 35 years of experience in memory technology, he holds 183 US patents and has published 59 papers in numerous prestigious IEEE conferences such as ISSCC, IEDM, Symposium on VLSI Technology and IMW. Prior to becoming General Chairman for IMW(International Memory Workshop) in 2012, he served as a member of the technical and organizing committee for 8 years.
In the same way the universe is ever-expanding, so is the "DataCosm" - the unique confluence of data, storage and compute. With 5G and AI accelerating the DataCosm's virtuous growth cycle, optimized storage and industry partnership are critical to addressing high performance, continuous bit growth and cost. Innovations in NAND technology address these needs at scale, with multiple technologies and manufacturing to keep pace with the evolving DataCosm and customer's needs. Solidigm and SK hynix are on the leading edge of SSD and NAND innovation, enabling our partners to deliver on the promise of the DataCosm across industries and applications.
Jim Elliott serves as Corporate Executive Vice President of Memory Sales at Samsung Semiconductor, Inc. He is responsible for a multi-billion dollar revenue sales organization that spans all memory products for Samsung Semiconductor in the United States.
Jim joined Samsung in 2001 and has held leadership positions in both marketing and sales during his tenure. A market visionary, he has helped champion the company's memory transition and market evolution to provide a synergistic product portfolio covering the server, cloud, PC, tablet, mobile, AR/VR and automotive markets.
Jim holds a Bachelor of Arts degree from the University of California at Davis and received a Master's degree in Business Administration from Cal Poly University in San Luis Obispo, CA.
Jin-Hyeok Choi leads the Solution Product R&D division, which delivers flash storage products ranging from MMC and UFS mobile memory devices eMMC to client-, server- and enterprise-class SSDs.
Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.
Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.
New and increasingly important data-centric workloads, such as real-time analytics, AI/ML, VR/AR, IoT, HPC, and cybersecurity, demand tremendous throughput at a reasonable price. The current memory/storage hierarchy of DRAM and flash cannot do the job alone. A new tier is needed that is persistent, high-throughput/low-latency, production-proven, low-cost, scalable, and simple to integrate into existing designs. Such a tier can provide a tremendous speed boost at an affordable cost. Use cases are already available for a wide variety of key applications, and results show major advances in speed, cost/performance ratio, power consumption, and scalability.
Gary Kotzur is Marvell's Storage CTO, leading the Storage Organization and Architecture Team within Marvell's Storage Product Group. Gary has over 25 years in the computer industry and was previously with Dell EMC prior to joining Marvell in 2020.
Gary's team is responsible for delivering the product architecture, technology vision and strategy for storage and memory products which includes controllers for HDDs, SSDs, accelerators, fibre channel and CXL devices. The Storage CTO team also directs emerging technology investigations, standards bodies and university technology engagements. Gary has a diverse background spanning semiconductor to system level design, with expertise in the areas of computer, storage and networking architecture. Additionally, he has initiated and been involved in a number of industry standards while being an active member on their boards.
Over his career, Gary has been granted 69 patents for systems design that includes computer, networking, storage and ASIC architectures, and he has an additional 18 patent applications pending. Gary holds a bachelor's degree in electrical engineering from Texas A&M University and a master's degree in electrical engineering from The University of Houston.
Jon Haswell is the Senior Vice President of Firmware in Marvell's Storage Products Group. In this role, he is responsible for leading the company's global firmware and software teams in support of Marvell's SSD, HDD, Fibre Channel and Ethernet storage products. He joined Marvell in 2018 as Vice President of Flash Firmware and subsequently, served as Vice President of Storage Firmware. Prior to Marvell, Jon worked at SK hynix as Vice President of Firmware, and previous to this, he was Senior Director of Firmware Development at Micron Technology. He also held senior director roles at LSI Corporation and Samsung Information Systems America, respectively. Jon began his career with IBM in its hard disk drive development organization and continued to serve in various roles of increasing managerial and technical responsibility in IBM's storage division for more than twenty years. His work included research and product development in multiple leading-edge storage technologies including distributed filing systems, interface standards, storage controllers and system architectures.
Jon holds a B.S. in Electrical and Electronic Engineering from Loughborough University in the United Kingdom, and has been awarded 15 patents in the areas of storage systems and technology.
With the demand for workloads to scale up, down and everywhere in between, public cloud and hybrid cloud environments are under pressure to provide the ultimate in performance while at the same time remaining cost-competitive. Designing the highest performing storage and memory infrastructure for all workloads remains an expensive proposition at cloud scale, often resulting in underutilized resources - there has to be a better way. Optimizing NVMe and CXL-based silicon solutions from both a hardware and firmware perspective is proving the be the key to success in driving the foundation for the most scalable data center infrastructure.
Andy Hsu is the Founder and CEO of NEO Semiconductor, a company focused on the development of innovative architectures for NAND flash and DRAM memory. Andy is responsible for the overall company strategy, execution, and technology innovation that fuels the company's growth. He has more than 25 years of experience in the semiconductor industry including positions as VP of Engineering and leader of R&D and Engineering Teams. This resulted in the development of more than 60 products in various non-volatile memories. Andy is an accomplished technology visionary and inventor of more than 120 granted U.S. patents. He performed research in the fields of Neural Networks and Artificial Intelligence (AI) while earning a master's degree in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) in New York. He earned a bachelor's degree from the National Cheng-Kung University in Taiwan.
CPUs and GPUs have made quantum leaps in computing speeds with acceleration of up to 60% every year. Yet, DRAM data latency improved about 30% over 20 years, while NAND flash became 3-5 time slower. The next wave of enterprise and consumer workloads will demand higher performance memory and storage solutions to better match computing speeds.
Architectural changes for memory and storage can overcome the limitations of conventional designs. The answer is in new architectures that can significantly reduce data latency while lowering power and improving throughput, respectively. We will explore visionary ways to design memory architectures and various innovative techniques that can fuel greater sustainability and accelerated performance for cloud and enterprise data centers while also enabling an entirely new generation of cost-effective consumer and mobile devices.
Pete Hazen is Vice President of Data Center Solution business at Microchip (Nasdaq: MCHP). In this role, Pete is responsible for storage, memory and compute connectivity solutions as well as SSD controller solutions for next generation data centers. Pete is a 35-year industry veteran with experience in silicon design and architecture, applications engineering and marketing, business development, strategy and management. Pete holds a Bachelor of Science degree in Electrical Engineering from the University of Wisconsin-Madison. He holds over 20 patents in hardware and software.
Data centers continue to have the formidable task of gaining control of their IT investment spend by improving operating efficiency, reducing complexity, and increasing scale in the face of evolving and varied workload requirements. New architectures have emerged to better utilize and optimize hardware assets spanning across compute, storage, and now memory tiers. Resource agility is essential to unlocking efficiencies and eliminating stranded and underutilized assets. We will explore the innovations on the leading edge of these flexible architectures, examine primary barriers to adoption, and highlight technologies that both the industry and vendors like us have delivered.
Gary Adams is Senior Director of Marketing at Silicon Motion. He leads a focused team in defining and promoting Enterprise controllers and development platforms that accelerate high performance, data center SSD development. Gary has over 20 years in providing innovate leadership storage products and business solutions addressing market application needs. He has held various marketing and sales management positions at Microchip, Microsemi, PMC-Sierra and IDT. He earned a BSEE and MSEE at CSU-Chico.
Fueled by unprecedented technology growth, new innovation engines in chip design and SSD firmware architectures are required to address next generation data center optimizations maximizing performance and capacity while reducing power and TCO. New SSD design needs to address the litany of new form factors, security threats, NAND technology transitions to QLC and beyond while supporting evolving standards. To face these challenges at speed, new approaches are needed in providing firmware design flexibility and scalability enabling differentiation while reducing development time to market.
Dr. Debendra Das Sharma is an Intel Senior Fellow in the Data Platforms and Artificial Intelligence Group and Chief Architect of the I/O Technology and Standards at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture.
Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.
Das Sharma has a bachelor's in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He is a frequent keynote speaker in various conferences and a Distinguished Lecturer in leading Universities. He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the Outstanding Engineer Award by IEEE Region 6 in 2021, and the Industrial Pioneer Award by IEEE Circuits and Systems in 2022.
The trends are undeniable, data growth is exploding, compute demands are unprecedented, system costs are increasing, and current data center infrastructure is under tremendous pressure. In order to address these challenges and unleash the full potential of data, Intel believes change begins at the underlying hardware architecture. This session will focus on Intel's efforts to drive disruption in the traditional memory-storage hierarchy and discuss the data-tiering evolution led by Optane technology. With the future always in mind, Intel has been building for the future of interconnected computing with the ecosystem. We will share our vision for delivering new CXL-enabled usages with Optane technology and how these new capabilities will deliver value to customers.
Matt Eastwood is Senior Vice President of IDC's enterprise infrastructure, cloud, telecom, security, developers, channels and enabling technology research groups. Mr. Eastwood and his team research people, process and technology trends affecting the enterprise technology marketplace worldwide. Mr. Eastwood first joined IDC in 2000 as part of the server team and his responsibilities have evolved and expanded during his tenure. In his current role, he leads a team of more than 100 analysts providing insights and analysis to IT suppliers, buyers, investors, and distributors through more than 75 syndicated research programs. Mr. Eastwood also leads IDC's BuyerView primary research programs which are focused on defining emerging trends in cloud, developers, service providers, edge, AI and security.
The last few years have pressure tested digital infrastructures around the globe while forcing business leaders to rethink the foundational importance of infrastructure as they seek the scale, agility and efficiency necessary to be a digitally driven enterprise. As the industry looks forward, organizations will continue to leverage technology to underpin every process, prioritize key business initiatives, and stabilize their value chain as the journey to overcome the economic shock we are facing in 2022 and beyond. Attend this keynote session with analyst Matt Eastwood, Senior Vice President at IDC, who will discuss the challenges and opportunities facing today's infrastructure market given the changes to global dynamics and customer priorities.
Scott is a recognized technology leader with proven practical technology expertise, year after year proven success that drives innovation, creative and edgy marketing strategies, and a consistent focus on tactical execution to achieve business strategies. At IBM, he leads a product marketing team responsible for being the voice of IBM Servers, Storage and Technical Services products and solutions in the market and the voice of the market in the products. Since joining IBM, Scott's has revised our go-to-market strategies, brought the storage brand to the forefront of the pan-IBM marketing and digital efforts, and championed some of the more successful marketing launches that have been made to date. Over the past 25 years, Scott has held senior positions with major storage vendors, most recently as Vice President of Product Marketing for the Pure Storage FlashArray portfolio. Prior to that, Scott held leadership positions in product management, product marketing, product development and strategy at Hitachi Vantara, HPE / HP Inc., NetApp and EMC. Prior to joining the storage industry, Scott left a successful start-up, worked as Software Engineering Manager for the Nation Aeronautics and Space Administration and served in the US Army. Scott holds a Bachelor and Master of Science in Computer Science from Columbia Southern University and an MBA from the University of N. Alabama. In his spare time, Scott is an avid SCUBA diver, diving instructor and underwater photographer.
Storage continues to play a critical role as the "data custodian" in enterprise operations and cyber resiliency strategies. In addition to providing containers where data is stored when not in main memory or cache, the storage layer is also responsible for providing safeguarding functions that help organizations recover from unusual events. While most enterprise storage solutions on the market today focus on response and recovery operations, at IBM we believe the first step in creating an information supply chain that cannot be breached is to imbue the storage array with device-level threat intelligence. Join us in this session where we discuss the integration of AI/ML models into our FlashCoreModules as an added computation storage service explicitly designed to identify and detect threat signatures and initiate automated response operations to protect the organization and its data from unauthorized access and use.
Doug Wong has over 35 years of experience designing and engineering NOR- and NAND-based devices at KIOXIA America, Inc. His responsibilities include systems engineering and new product definitions for flash-based devices, and detailing these new products to design engineers. Doug also writes applications notes and technical documentation, and works with customers to solve their engineering problems. He holds a BSEE from California Polytechnic State University, and an MSEE in Semiconductor Physics from UCLA.
Dr. Luca Fasoli is responsible for the strategy and the development of Western Digital's solid-state memory technologies. He previously held engineering management positions at Waferscale Integration, STMicroelectronics, Matrix Semiconductor, and at SanDisk after its acquisition of Matrix.
As a 25-year industry veteran and IEEE Senior Member, Dr. Fasoli has worked on a variety of non-volatile memory technologies and solid-state storage products, leading product development teams from concept definition to mass production. He has published many technical papers and holds over 90 U.S. patents. His doctorate and master's degrees in Electronic Engineering are from the Polytechnic University of Milan, and he completed the Engineering Leadership Professional Program at UC Berkeley. Luca is based at the company's Milpitas, CA campus.
Santosh Kumar has held various leadership roles at SK Hynix. He represents the company in standards related to SSDs, and plays a critical role in SSD product planning. Santosh was previously the Principal Engineering Technologist at Dell Drive Engineering, and was responsible for leading SSD, NVM technologies, and storage media card strategy, along with advanced engineering evaluation. He has over 22 years' experience in the SOC, system, and storage industries in architecture and management roles, and has led global engineering teams. Santosh holds a Masters in Electronic Instrumentation from the NIT Warangal, India, and has over 10 patents in the field of storage and data security.
Paul Saffo is a Silicon Valley-based forecaster who studies the dynamics of large-scale, long-term technological change, and he has served as an advisor to corporate, NGO and governmental clients worldwide. He is an Adjunct Professor in Stanford's School of Engineering, a non-resident Senior Fellow at the Atlantic Council, and a Fellow of the Royal Swedish Academy of Engineering Sciences. Paul was founding Chair of Samsung's SAIT Science Board, and he has served on technology advisory boards at AT&T Bell Labs and Motorola. He holds degrees from Harvard College, Cambridge University, and Stanford University.
Paul Saffo will lead a discussion with key representatives from the world's top flash memory manufacturers will discuss topics related to NAND Flash Memory, including key events over the last 35 years since its introduction, applications that wouldn't exist if NAND flash had not been invented, the new applications that NAND will be enabling, and the next challenges that are expected to continue innovation in NAND Flash and forms of memory.